Semiconductor Electronics — NEET High-Yield Notes
Semiconductors possess electrical conductivity between that of conductors and insulators. Their conductivity can be precisely controlled by temperature, light, and chemical doping.
1. Energy Band Classification & Doping
Fig 1: Energy Band Gaps for Conductors (Overlapping), Semiconductors (Eg < 3 eV), and Insulators (Eg > 3 eV)
- Intrinsic Semiconductors: Pure Si or Ge. Electrical conduction is due to thermal generation of electron-hole pairs:ne = nh = ni | ne ⋅ nh = ni2 (Mass Action Law)
- Extrinsic Semiconductors: Doped semiconductors:
- n-type: Doped with Pentavalent impurities (P, As, Sb). Electrons are majority carriers: ne ≈ ND >> nh. Donor energy level lies just below the conduction band.
- p-type: Doped with Trivalent impurities (B, Al, In, Ga). Holes are majority carriers: nh ≈ NA >> ne. Acceptor energy level lies just above the valence band.
NEET Fundamental Invariant: Extrinsic semiconductors (both n-type and p-type) are ELECTRICALLY NEUTRAL overall, because each neutral dopant atom contributes a free carrier along with an equal fixed nuclear charge!
2. p-n Junction Diode & Biasing
When a p-type and n-type material meet, diffusion of holes and electrons creates a fixed space-charge Depletion Layer and a built-in potential barrier (V0 ≈ 0.7 V for Si, 0.3 V for Ge).
Fig 2: Forward Bias (Barrier Decreases, Depletion Narrows) vs Reverse Bias (Barrier Increases, Depletion Widens)
- Forward Bias: Positive battery terminal to p-side, negative to n-side. Depletion width decreases, barrier drops to (V0 - V). Large diffusion current flows in mA.
- Reverse Bias: Positive terminal to n-side, negative to p-side. Depletion layer widens, barrier increases to (V0 + V). Negligible drift current flows in μA.
3. Rectifiers & Zener Diode Voltage Regulator
Fig 3: Diode I-V Curve and Half-Wave vs Full-Wave Rectifier Circuits
A. Rectifiers
- Half-Wave Rectifier: 1 diode. Output frequency = fin (50 Hz). Max efficiency η = 40.6%, ripple factor γ = 1.21.
- Full-Wave Rectifier: 2 diodes (center-tapped) or 4 diodes (bridge). Output frequency = 2 fin (100 Hz for 50 Hz input). Max efficiency η = 81.2%, ripple factor γ = 0.48.
B. Zener Diode as Voltage Regulator
A heavily doped p-n junction with a thin depletion layer that operates continuously in the reverse breakdown region without damage. Across the breakdown voltage VZ, current changes drastically while voltage remains rock solid. It is always connected in reverse bias in parallel with the load.
4. Logic Gates & De Morgan's Theorems
Fig 4: Standard Logic Gates (AND, OR, NOT, NAND, NOR, XOR) and Truth Tables
- Universal Gates: NAND and NOR gates are universal because ANY Boolean function or gate can be realized using only NAND or only NOR gates.
- De Morgan's First Law: A + B = A ⋅ B (NOR gate is equivalent to Bubbled AND gate).
- De Morgan's Second Law: A ⋅ B = A + B (NAND gate is equivalent to Bubbled OR gate).
Semiconductor Electronics — Formula Matrix & 20 Golden Facts
Master Formula Matrix
| Concept | Formula | Key NEET Exam Point |
|---|---|---|
| Mass Action Law | ne ⋅ nh = ni2 | Valid in thermal equilibrium for intrinsic & extrinsic |
| Conductivity | σ = e (ne μe + nh μh) | μe > μh in all semiconductors |
| Band Gap Photon | Eg = h cλ = 1240 eV⋅nmλ | Determines LED emission color |
| Half-Wave Freq | fout = fin | ηmax = 40.6%, ripple = 1.21 |
| Full-Wave Freq | fout = 2 fin | ηmax = 81.2%, ripple = 0.48 |
| Zener Current | IZ = IS - IL | IS = (Vin - VZ) / RS |
| Dynamic Resistance | rd = ΔVΔI | Reciprocal of I-V curve slope |
| De Morgan 1 | A + B = A ⋅ B | NOR = Bubbled AND |
| De Morgan 2 | A ⋅ B = A + B | NAND = Bubbled OR |
20 Golden NEET Must-Know Facts & Traps
1. Both n-type and p-type semiconductors are ELECTRICALLY NEUTRAL. They carry zero net electric charge.
2. At absolute zero (0 K), an intrinsic semiconductor has zero electrons in conduction band and behaves as a perfect insulator.
3. Electron mobility is always greater than hole mobility: μe > μh, because electrons move in the conduction band while holes move in the valence band through covalent bond breaking.
4. Temperature coefficient of resistance for semiconductors is negative (α < 0): As temperature increases, resistance decreases exponentially!
5. Energy band gap of Silicon is 1.1 eV; Germanium is 0.7 eV; Gallium Arsenide (GaAs) is 1.43 eV.
6. Carbon, Silicon, and Germanium all belong to Group 14, but Carbon (Diamond) is an insulator (Eg ≈ 5.4 eV) due to very small atomic size and tightly bound electrons.
7. Depletion layer in a p-n junction contains immobile donor ions (n-side) and immobile acceptor ions (p-side), completely devoid of mobile charge carriers.
8. Under forward bias, the depletion layer narrows and barrier height decreases to (V0 - V). Under reverse bias, the depletion layer widens and barrier increases to (V0 + V).
9. Current in forward bias is predominantly due to majority carrier diffusion (mA). Current in reverse bias is due to minority carrier drift (μA).
10. Zener diode is operated in reverse breakdown region. Zener breakdown occurs in heavily doped junctions due to strong electric field (≈ 106 V/m) rupturing bonds directly.
11. Avalanche breakdown occurs in lightly doped diodes with wide depletion layers due to collision ionization by accelerated minority carriers.
12. Zener voltage regulator: If input voltage increases, the current through the Zener diode IZ increases, but voltage across the load remains strictly constant at VZ.
13. Photodiode is operated under reverse bias because fractional change in minority carrier current upon illumination is much easier to observe than in majority carriers.
14. Solar cell operates under zero external bias (generates photovoltage via built-in field separation of electron-hole pairs).
15. LED is always operated in forward bias. Emitted photon energy hν ≈ Eg. Silicon and Germanium are NOT used for LEDs because they are indirect bandgap semiconductors (recombination produces heat, not light).
16. For a 50 Hz AC mains input, output frequency of a half-wave rectifier is 50 Hz, but for a full-wave rectifier it is 100 Hz (2f)!
17. Maximum theoretical efficiency of a half-wave rectifier is 40.6%; for a full-wave rectifier it is 81.2%.
18. Universal gates: NAND and NOR gates can be combined to reproduce all other logic operations (AND, OR, NOT).
19. To make a NOT gate from a NAND gate, simply tie both inputs together (A = B).
20. XOR gate output is 1 when inputs are different (odd parity): Y = A ⋅ B' + A' ⋅ B. Output is 0 when inputs are identical.
Semiconductor Electronics — 8 Solved NEET Numericals (3-Box Layout)
Problem 1: Mass Action Law & Minority Carrier Density
Given: Intrinsic carrier concentration of silicon ni = 1.5 × 1016 m-3. It is doped with Indium (trivalent, acceptor) to a density NA = 4.5 × 1022 m-3. Find the electron density ne.
Step-by-Step Calculation:
Since it is p-type, majority hole density nh ≈ NA = 4.5 × 1022 m-3.
By Mass Action Law: ne ⋅ nh = ni2.
ne = ni2nh = (1.5 × 1016)24.5 × 1022 = 2.25 × 10324.5 × 1022 = 5.0 × 109 m-3.
Since it is p-type, majority hole density nh ≈ NA = 4.5 × 1022 m-3.
By Mass Action Law: ne ⋅ nh = ni2.
ne = ni2nh = (1.5 × 1016)24.5 × 1022 = 2.25 × 10324.5 × 1022 = 5.0 × 109 m-3.
NEET Shortcut: ne = ni2 / NA. The minority carrier density drops drastically upon heavy doping!
Problem 2: Full-Wave Rectifier Ripple Frequency
Given: A full-wave bridge rectifier is supplied with 60 Hz AC voltage. What is the fundamental frequency of the ripple in the rectified output?
Step-by-Step Calculation:
In a full-wave rectifier, both positive and negative half-cycles of input AC are converted into unidirectional pulses.
Therefore, two output pulses occur per input cycle.
fripple = 2 × fin = 2 × 60 Hz = 120 Hz.
In a full-wave rectifier, both positive and negative half-cycles of input AC are converted into unidirectional pulses.
Therefore, two output pulses occur per input cycle.
fripple = 2 × fin = 2 × 60 Hz = 120 Hz.
NEET Trap Alert: For half-wave rectifier fout = fin (60 Hz). For full-wave rectifier fout = 2 × fin (120 Hz).
Problem 3: Zener Diode Voltage Regulator Calculation
Given: A Zener diode with breakdown voltage VZ = 10 V is used in a regulator circuit with series resistor RS = 200 Ω. Input unregulated voltage Vin = 15 V, and load resistor RL = 1 kΩ (1000 Ω). Find Zener current IZ.
Step-by-Step Calculation:
Voltage across load VL = VZ = 10 V.
Load current IL = VZRL = 10 V1000 Ω = 0.01 A = 10 mA.
Voltage drop across series resistor: VRS = Vin - VZ = 15 - 10 = 5 V.
Total series current IS = VRSRS = 5 V200 Ω = 0.025 A = 25 mA.
By Kirchhoff's current law: IS = IZ + IL → IZ = IS - IL = 25 mA - 10 mA = 15 mA.
Voltage across load VL = VZ = 10 V.
Load current IL = VZRL = 10 V1000 Ω = 0.01 A = 10 mA.
Voltage drop across series resistor: VRS = Vin - VZ = 15 - 10 = 5 V.
Total series current IS = VRSRS = 5 V200 Ω = 0.025 A = 25 mA.
By Kirchhoff's current law: IS = IZ + IL → IZ = IS - IL = 25 mA - 10 mA = 15 mA.
NEET Shortcut: IZ = (Vin - VZ)/RS - VZ/RL = 25 mA - 10 mA = 15 mA.
Problem 4: Dynamic Forward Resistance of Diode
Given: Current through a forward-biased silicon diode increases from 10 mA to 30 mA when voltage increases from 0.70 V to 0.75 V. Find dynamic resistance.
Step-by-Step Calculation:
ΔV = 0.75 - 0.70 = 0.05 V.
ΔI = 30 mA - 10 mA = 20 mA = 20 × 10-3 A.
Dynamic resistance rd = ΔVΔI = 0.05 V20 × 10-3 A = 5020 = 2.5 Ω.
ΔV = 0.75 - 0.70 = 0.05 V.
ΔI = 30 mA - 10 mA = 20 mA = 20 × 10-3 A.
Dynamic resistance rd = ΔVΔI = 0.05 V20 × 10-3 A = 5020 = 2.5 Ω.
NEET Shortcut: Forward dynamic resistance of a diode is very small (≈ a few ohms).
Problem 5: Wavelength of Light Emitted by LED
Given: An LED is fabricated from a semiconductor with band gap Eg = 1.8 eV. Find the wavelength λ of emitted light. (hc ≈ 1240 eV⋅nm)
Step-by-Step Calculation:
Eg = h cλ → λ = h cEg.
λ = 1240 eV⋅nm1.8 eV = 688.9 nm ≈ 690 nm (Red light).
Eg = h cλ → λ = h cEg.
λ = 1240 eV⋅nm1.8 eV = 688.9 nm ≈ 690 nm (Red light).
NEET Shortcut: λ (in nm) = 1240 / Eg (in eV). 1240 / 1.8 ≈ 689 nm!
Problem 6: Identification of Logic Gate from Truth Table
Given: A circuit with two inputs A and B gives output Y = 0 only when A = 1 and B = 1. For all other input combinations (0,0; 0,1; 1,0), Y = 1. Identify the gate.
Step-by-Step Calculation:
An AND gate gives Y = 1 only when A = 1 and B = 1.
Here, Y is the exact complement of AND:
Y = A ⋅ B.
Therefore, the gate is a NAND gate.
An AND gate gives Y = 1 only when A = 1 and B = 1.
Here, Y is the exact complement of AND:
Y = A ⋅ B.
Therefore, the gate is a NAND gate.
NEET Shortcut: Inverted AND = NAND!
Problem 7: Silicon Diode in Series with Resistor Circuit
Given: A silicon diode (barrier potential V0 = 0.7 V) is connected in series with a resistor R = 100 Ω across a 4.7 V DC source in forward bias. Find the current.
Step-by-Step Calculation:
Voltage drop across resistor: VR = Vsource - Vdiode = 4.7 V - 0.7 V = 4.0 V.
Current I = VRR = 4.0 V100 Ω = 0.04 A = 40 mA.
Voltage drop across resistor: VR = Vsource - Vdiode = 4.7 V - 0.7 V = 4.0 V.
Current I = VRR = 4.0 V100 Ω = 0.04 A = 40 mA.
NEET Shortcut: Always subtract the diode barrier voltage (0.7 V for Si) from the supply voltage before applying Ohm's law!
Problem 8: Universal NAND Gate Implementation of OR Gate
Given: How many 2-input NAND gates are required to construct an OR gate?
Step-by-Step Calculation:
By De Morgan's Law: A + B = A ⋅ B.
1. Invert A using 1 NAND gate (inputs tied together) → A'.
2. Invert B using 1 NAND gate (inputs tied together) → B'.
3. Feed A' and B' into a 3rd NAND gate → (A' ⋅ B')' = A + B.
Total NAND gates required = 3 gates.
By De Morgan's Law: A + B = A ⋅ B.
1. Invert A using 1 NAND gate (inputs tied together) → A'.
2. Invert B using 1 NAND gate (inputs tied together) → B'.
3. Feed A' and B' into a 3rd NAND gate → (A' ⋅ B')' = A + B.
Total NAND gates required = 3 gates.
NEET Universal Matrix:
To make NOT: 1 NAND | 1 NOR
To make AND: 2 NAND | 3 NOR
To make OR: 3 NAND | 2 NOR
To make XOR: 4 NAND | 5 NOR
To make NOT: 1 NAND | 1 NOR
To make AND: 2 NAND | 3 NOR
To make OR: 3 NAND | 2 NOR
To make XOR: 4 NAND | 5 NOR
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